module datapath
		(
		clock, resetn,
		
		load_pc, cnten_pc, sclr_pc,
		load_opc, load_opr,
		load_a, cntdn_a, sclr_a,
		load_b, cntdn_b, sclr_b,
		load_cntref, cnten_tmr, sclr_tmr,
		init_porta, load_porta, INITA,
		init_portb, load_portb, INITB,
		sel_portb, PBADDR,
		
		zero_a, zero_b,
		
		branch, decabnz, decbbnz,
		ioset, loada, loadb,
		swait,
		ramp, rsram, rlta,
		int_tmr,
		
		PORTA, PORTB
		);
input			clock, resetn;
input			load_pc, cnten_pc, sclr_pc;
input			load_opc, load_opr;
input			load_a, cntdn_a, sclr_a;
input			load_b, cntdn_b, sclr_b;
input			load_cntref, cnten_tmr, sclr_tmr;
input			init_porta, load_porta;
input	[11:0]	INITA;
input			init_portb, load_portb;
input	[15:0]	INITB;
input			sel_portb;
input	[5:0]	PBADDR;

output			zero_a, zero_b;
output			branch, decabnz, decbbnz;
output			ioset, loada, loadb;
output			swait;
output			ramp, rsram, rlta;
output			int_tmr;
output	[11:0]	PORTA;
output	[15:0]	PORTB;

wire	[27:0]	DBUS;
wire	[31:0]	IBUS;
wire	[7:0]	ABUS;

wire	[3:0]	rOPC;
wire	[27:0]	rA;
wire	[27:0]	rB;
wire	[27:0]	rCNTREF;
wire	[27:0]	rTMR;

wire	[15:0]	PBVAL;
wire	[15:0]	PBSRC;


lpm_pc			PC		(.clock(clock), .cnt_en(cnten_pc), .sclr(sclr_pc), .sload(load_pc),
						 .aclr(~resetn),
						 .data(DBUS[7:0]), .q(ABUS));

lpm_instrom		INSTROM	(.address(ABUS), .q(IBUS));

opcreg			OPC		(.clock(clock), .resetn(resetn), .load(load_opc),
						 .DATA(IBUS[31:28]), .Q(rOPC));

opcdec			OPCDEC	(.DATA(rOPC),
						 .branch(branch), .decabnz(decabnz), .decbbnz(decbbnz),
						 .ioset(ioset), .loada(loada), .loadb(loadb),
						 .swait(swait),
						 .ramp(ramp), .rsram(rsram), .rlta(rlta));

genreg			OPR		(.clock(clock), .resetn(resetn), .load(load_opr),
						 .DATA(IBUS[27:0]), .Q(DBUS));

lpm_acc			A		(.clock(clock), .cnt_en(cntdn_a), .sclr(sclr_a), .sload(load_a),
						 .aclr(~resetn),
						 .data(DBUS), .q(rA));

assign			zero_a = ~(|rA);

lpm_acc			B		(.clock(clock), .cnt_en(cntdn_b), .sclr(sclr_b), .sload(load_b),
						 .aclr(~resetn),
						 .data(DBUS), .q(rB));

assign			zero_b = ~(|rB);

genreg			CNTREF	(.clock(clock), .resetn(resetn), .load(load_cntref),
						 .DATA(DBUS), .Q(rCNTREF));

lpm_tmr			TMR		(.clock(clock), .cnt_en(cnten_tmr), .sclr(sclr_tmr),
						 .aclr(~resetn), .q(rTMR));

lpm_comp		TMRCOMP	(.dataa(rTMR), .datab(rCNTREF), .ageb(int_tmr));

portareg		PORTAREG1(.clock(clock), .resetn(resetn), .init(init_porta), .load(load_porta),
						 .INIT(INITA), .DATA(DBUS[11:0]), .Q(PORTA));

portbreg		PORTBREG1(.clock(clock), .resetn(resetn), .init(init_portb), .load(load_portb),
						  .INIT(INITB), .DATA(PBSRC), .Q(PORTB));

assign			PBSRC = (sel_portb)? PBVAL : DBUS[27:12];

lpm_pbrom		PBROM	(.address(PBADDR), .q(PBVAL));

endmodule